Staff Digital Design Engineer - SOC

Austin, TX, United States

Staff Digital Design Engineer - SOC page is loaded Staff Digital Design Engineer - SOC Apply locations Austin time type Full time posted on Posted 2 Days Ago job requisition id 19842 We are Silicon Labs.We are a leader in secure, intelligent wireless technology for a more connected world.Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives.

Staff Digital Design Engineer - SOC

Austin, TX

Meet the Team

The IoT Digital Design team is a state-of-the-art IC design team focused on producing world class Wireless MCU SoCs. The architecture specification, design, verification, emulation, and implementation of the Wireless MCU SoCs are all the responsibilities of the IoT Digital team. These SoCs include an embedded CPU system with analog and digital peripherals, advanced security, advanced power management, and best in class radios to support a wide range of wireless IoT applications and standards. We strive to provide advanced technology solutions through innovation in custom RISC-V Cores and AI/ML components.

Responsibilities

The Role As a Staff Digital Design Engineer you will develop world class, highly integrated, low power, System on a Chip devices to serve the IoT wireless market.

Responsibilities include the following:

Develop complex SOC/chip Architectures with multiple processors, digital and mixed signal subsystems, multiple power, and clock domains with a goal towards optimizing power for specific customer scenarios.

Collaborate with System Engineers and Product Management to drive definition of SOC devices to meet product requirements.

Lead small teams of design engineers to architect, design and verify digital subsystems.

RTL design of modules through System Verilog HDL coding, adhering to quality standards.

Prepare and hold architecture, design, and verification reviews with technical staff throughout project lifecycle

SOC level configuration and integration of digital and mixed-signal IPs. Examples include embedded processors, memory and controllers, busses, power and clocking systems, security systems, machine learning, radio systems, analog IP, and pads.

Perform logic synthesis, full chip timing and power analysis to optimize designs for key customer scenarios.

Pre-silicon verification utilizing a combination of block/chip-level test benches.

Validation/bring-up of designs on silicon, providing support to cross-functional teams

Skills You Will Need

Master’s degree in Electrical Engineering

10-20 years of professional experience in digital CMOS IC design

Minimum Qualifications

Demonstrated ability to lead small teams designing complex digital subsystems

Verilog RTL design with demonstrated experience of taking designs through the silicon development lifecycle to production

Knowledge of embedded processor systems and C coding

Experience with logic simulators for both RTL and gate-level simulation, design/waveform browsers, and power analysis tools

Experience with logic synthesis and timing constraints

Experience in working with backend team to optimize design for power performance and area.

Experience in working with analog and mixed signal designs, to support design integration and verification of these subsystems in SOC.

Experience with scripting and automation. Knowledge of Python, Perl, and Tcl

Experience with revision control and configuration management systems (such as Perforce, Git, Methodics)

Excellent written and verbal communications skills

Demonstrated ability to generate high output in a self-driven manner

Benefits & Perks

You can look forward to the following benefits:

Great medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental and vision plans

Highly competitive salary

401k plan with match and Roth plan option

Equity rewards (RSUs)

Employee Stock Purchase Plan (ESPP)

Life/AD&D and disability coverage

Flexible spending accounts

Adoption assistance

Back-Up childcare

Additional benefit options (Commuter benefits, Legal benefits, Pet insurance)

Flexible PTO schedule

3 paid volunteer days per year

Charitable contribution match

Tuition reimbursement

Free downtown parking

Onsite gym

Monthly wellness offerings

Free snacks

Monthly company updates with our CEO

# LI-KB1

#LI-Hybrid

The annualized base pay range for this role is expected to be between $133,500 - $247,928 USD. Actual base pay could vary based on factors including but not limited to experience, geographic location where work will be performed and applicant’s skill set. The base pay is just one component of the total compensation package for employees. Other rewards may include an annual cash bonus, equity package and a comprehensive benefits package. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

Similar Jobs (3) Staff System Modeling Engineer locations Austin time type Full time posted on Posted 12 Days Ago Staff FPGA Emulation Engineer locations Austin time type Full time posted on Posted 3 Days Ago Staff Verification Engineer locations Austin time type Full time posted on Posted 12 Days Ago

#J-18808-Ljbffr