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Ericsson
Austin, TX, United States
Grow with us About this opportunity: This position is an onsite opportunity in Austin, Texas. It is not open for remote work. This position requires several years of in industry, hands on experience. The Ericsson Radio and Baseband Products have our ASICs as their backbone. Our ASICs continuously push limits in size, complexity, power, performa
Job Source: EricssonNet2Source Inc.
Austin, TX, United States
Net2Source Inc. is an award-winning total workforce solutions company recognized by Staffing Industry Analysts for our accelerated growth of 300% in the last 3 years with over 5500+ employees globally, with over 30+ locations in the US and global operations in 32 countries. We believe in providing staffing solutions to address the current talent ga
Job Source: Net2Source Inc.Verilab
Austin, TX, United States
Job Description Job Description Job Summary We invite you to join our highly motivated team of consultants, providing clients with the very best in verification. You will be exposed to a diverse range of designs and application areas. We work on leading edge Audio, Automotive, Comms, Processors, Space, Video and more. You will have the opportuni
Job Source: VerilabACL Digital
Austin, TX, United States
Position: Design Verification Engineer Location: Austin, TX (Onsite) Duration: Long-term Position Overview: 12+ years of relevant experience in Verification. Experience with System Verilog and UVM. Deep understanding of constrained randomization and the development of efficient test suites. Work with DV team and designers to build verification env
Job Source: ACL DigitalMeta Inc
Austin, TX, United States
Summary: Reality Labs focuses on delivering Meta's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Meta’s Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the
Job Source: Meta IncPlatform Recruitment
austin, tx
Design Verification Engineer – Competitive Salary – Austin, Tx OR Santa Clara, California I’m working with an exciting RISC-V Start Up who are keen to onboard full-time SOC Verification Engineers. I’m looking for individuals with a range of experience levels. Whether you’re a beginner or a seasoned professional, I’d love to chat! What you'll do: W
Job Source: Platform RecruitmentMastech Digital
austin, tx
Job Title : Design Verification Engineer Location: Austin, TX Requirements • 5-15 year’s industry experience in a design verification role. • Proficient in System Verilog/UVM/OVM, OOP/C++ • Knowledge of GPU, experience with Shader, Texture, or Memory System a plus • Experience with code coverage and functional coverage driven verification method
Job Source: Mastech DigitalVoragotech
Austin, TX, United States
Do you love Space and want to leave your technical mark on exploring mankind’s next frontier? Does being a part of working with clients designing the next state-of-the-art spacecraft for near-earth orbit, Mars, Lunar and deep space explorations inspire you? Investment in Space organizations is at an all-time high, and you could have a seat at the t
Job Source: VoragotechAustin, TX, United States
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an unusually hardworking design verification engineer. As a member of our multifaceted group, you will have the rare and great opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day.This role is for a DV engineer who will enable us to produce fully functional first silicon for Analog/Digital mixed-signal designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
Key Qualifications
Advanced knowledge of SystemVerilog and UVM
Experience developing scalable and portable test-benches
Experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, gate level simulations
Experience with serial protocols such as PCIe or USB
Experience with IP verification method
Deep knowledge with IPs developments such as PHYs, PLLs etc.
In lieu of UVM knowledge, C/C++ experienced level knowledge
Excellent knowledge of one of the scripting languages: Python, Perl, TCL
Proven knowledge of formal verification methodology
Description In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are expected to: Develop detailed test and coverage plans based on the micro-architecture Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under your care. Execute verification plans, including design bring-up, DV environment bring-up, regression enabling all features under your care, and debug of the test failures. Develop block, IP and SoC level test-benches Track and report DV progress using a variety of metrics, including bugs and coverage. Develop IP simulation environment, and work closely with analog team to ensure overall bug-free IP design.
Education & Experience
BS degree in technical discipline with minimum 10 years of relevant experience.Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.
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Design Verification Engineer jobs in Austin, TX, United States
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